| PART |
Description |
Maker |
| CY7C1623KV18 CY7C1623KV18-333BZXC |
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
|
Cypress Semiconductor
|
| R1QEA4418RBG-20IA0 R1QEA4436RBG-20IB0 R1QEA4436RBG |
144-Mbit DDR?II SRAM 2-word Burst Architecture ( 2.5 Cycle Read latency ) with ODT
|
Renesas Electronics Corporation
|
| CY7C1529JV18-250BZXC CY7C1529JV18-250BZXI CY7C1529 |
8M X 9 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1429AV18 CY7C1422AV18 |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture(2字Burst结构36-Mbit DDR-II SIO SRAM) 36兆位的DDR - II二氧化硅的SRAM 2字突发架构（2字突发结36 -兆位的DDR - II二氧化硅的SRAM
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture(2字Burst结构6-Mbit DDR-II SIO SRAM) 36兆位的DDR - II二氧化硅的SRAM 2字突发架构（2字突发结36 -兆位的DDR - II二氧化硅的SRAM
|
Cypress Semiconductor Corp.
|
| UPD42S16100LLA-A80 UPD42S16100LG3-A80-7JD UPD42S17 |
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
9-Mbit (256K x 32) Pipelined DCD Sync SRAM
9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync SRAM
x1 Fast Page Mode DRAM x1快速页面模式的DRAM
|
TOKO, Inc.
EPCOS AG
|
| CY7C1992BV18-167BZXC CY7C1992BV18-300BZC CY7C1992B |
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 2M X 9 DDR SRAM, 0.5 ns, PBGA165
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 2M X 9 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1523AV18-200BZI CY7C1523AV18-300BZI CY7C1524AV |
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 2M X 36 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 4M X 18 DDR SRAM, 0.5 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| HM66AEB18204BP-30 |
36 MBit DDR II SRAM 4 Word Burst
|
Renesas Technology / Hitachi Semiconductor
|
| CY7C1645KV18 CY7C1643KV18-450BZI CY7C1643KV18-400B |
144-Mbit QDR? II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress Semiconductor
|
| CY7C1316KV18 |
18-Mbit DDR II SRAM Two-Word Burst Architecture
|
Cypress Semiconductor
|
